1. Field of the Invention
The present invention relates to a treatment method and inspection method of a semiconductor wafer on which a device pattern is formed, a semiconductor device development method and a semiconductor wafer treatment apparatus, and it relates, for example, to a quantitative evaluation and pretreatment of a crystal defect such as a dislocation occurred on the semiconductor wafer.
2. Related Background Art
During manufacture of a semiconductor device, heat stress and film stress occurring in a device manufacturing process lead to a dislocation which deteriorates characteristics of the semiconductor device and causes such troubles as in a leak current and a breakdown voltage. To develop processes in which no dislocations occur, a wafer (TEG (Test Element Group) wafer) on which a semiconductor device is manufactured has heretofore been divided into a plurality of chips as shown in FIG. 14. A device film structure on a chip selected as a sample is removed by use of a chemical solution and subjected to selective etching to let out a crystal defect (dislocation), and then an etch pit is evaluated by use of a scanning electron microscope (hereinafter simply referred to as an SEM), an optical microscope and the like to qualitatively find the defect, thereby correcting process conditions, circuit patterns and the like on the basis of the evaluation.
It should be noted that the selective etching generally makes it possible to observe various kinds of crystal defects such as an oxidation-induced stacking fault (OSF) and a bulk micro defect (EMD) present in a wafer due to an oxygen precipitated material or the like, but evaluation of a dislocation mainly induced in a process will be described below as an example.
Furthermore, as disclosed in Japanese Patent Laid Open (kokai) No. 11 (1999)-54579 (FIG. 1 and p. 3) and Japanese Patent Laid Open (kokai) No. 8 (1996)-191090 (p. 5 to p. 7, FIG. 1), evaluation of a crystal defect in a state of a semiconductor wafer is also known, but both of the disclosures offer evaluation of a semiconductor wafer state before a device is formed.
The evaluation method described above in which the semiconductor is divided into pieces takes time for evaluation and provides a narrow evaluation range, so that when a dislocation occurs unevenly in a semiconductor wafer surface and when a dislocation occurs at a density below a certain density, frequent overlooking takes place and there is a lack of quantitativity, thus posing a problem that the evaluation can not be used as a guideline for process improvement. Other than the method described above, means for a wide-ranging evaluation of the dislocation caused in the device manufacturing process include an X-ray topograph method. However, this method provides a low resolution of several um whereas the design rule has been reduced (to 0.1 um) due to high integration of recent devices, which makes minute dislocations to be overlooked, thus making the method unusable after all. Further, since the X-ray is used, penetration depth thereof is several um even by use of a reflection method (Berg-Barrett method), it is thus difficult to take out only dislocations in a device active area, the recent depth of which is 1 um or less.
Next, observation by microscope of an etch pit of a dislocation due to the selective etching, which is carried out when a quantitative evaluation is made on a crystal defect such as dislocation, and data analysis thereof will be described.
In a manufacturing process of a semiconductor device using a silicon single crystal substrate, a crystal defect (dislocation) occurs depending on a three-dimensional structure (shape, size, film thickness) of a device and on process conditions, which is a cause of a leak system trouble. The cause of this dislocation is dependent on a pattern and process of a product. Such cases are reported that the dislocation has been caused formerly by stress during oxidation of LOCOS, and even by excessive stress of an embedded material (SiO2) in recent STI (shallow trench isolation). On the other hand, the dislocation often occurs due to implantation of ions which are one kind of charged particles and also due to plasma damage. An LDD (lightly doped drain) process in a transistor will be mainly described here. However, it is noted that the crystal defect in the present specification is not limited to the process described above but includes all dislocations introduced to a product or a semiconductor wafer during manufacture.
A recent MOS transistor needs an LDD structure to prevent deterioration due to hot electrons, and as shown in FIG. 15A, for example, when source/drain areas are formed, a spacer (hereinafter referred to as a sidewall) 201 of a silicon nitride film (SiN) or the like is utilized as a sidewall material for a gate to form a low concentration impurities area prior to a high concentration impurities area. This increases stress of a lower part of the sidewall, and a dislocation occurs in order to reduce this stress, and the dislocation further grows as shown in FIG. 15B to penetrate a diffusion area and a well joint.
Furthermore, a long expanding dislocation (hereinafter abbreviated as a dislocation) that runs into a depletion layer increases a leak current and has an influence on a yield ratio of elements. In addition, in a silicon semiconductor substrate having source/drain areas for a micro device, dislocations can often occur on a periphery of edges of gate conductors and wires where ions are implanted in a large dose amount in a process where silicon amorphousized by ion implantation is recrystallized during activation anneal.
A method of enabling direct observation by use of a TEM (transmission electron microscope) is a typical evaluation method of the dislocation, but an observation area within a semiconductor wafer surface is significantly small, which poses a disadvantage that there is a risk of mistaking an overall tendency. On the contrary, heretofore, such a technique has long been adopted wherein the etch pit (see FIG. 15C) created by etching in a chemical solution which has high selectivity to the dislocation is detected and counted by use of the microscope (optical microscope, SEM). However, the number of chips that can be observed a day through manual labor by an operator is several chips at most within a surface per semiconductor water, giving a limit in terms of time. Therefore, such a method has been conceived that utilizes an automatic defect evaluation device to detect a defect by use of the optical and electronic microscope and to judge and extract the defect with a calculator algorithm for image recognition. However, if such an automatic defect evaluation device is applied to pit observation after the same kind of selective etching, the following problems are caused.
With regard to positions where the dislocation occurs, stress extremely concentrates on a periphery of a point (crossing point) at which the gate conductor and an element separation oxide film (such as LOCOS, improved LOCOS, STI) cross, and in a worst case, the dislocation may occur in all cells including a transistor and the like. The reason why the dislocation (crystal defect induced in a process) occurs and grows on the highly integrated device is that local high stress is applied during heat treatment. Therefore, these dislocations generally occur in the same place of the device pattern which is repeated periodically. For example, as shown in FIG. 16, with regard to evaluation of a dislocation located in an evaluation area EA201 of a pattern within a observed chip, when evaluation is performed by use of an image recognition method in which a reference area RA201 in an adjacent pattern or adjacent chip is compared with the evaluation area EA201 by an automatic evaluation so as to extract a difference between them, the patterns both having a dislocation in the same place are compared, as a result, a judgement “no defect” is made in this case. Current devices using such a method (die-to-die or cell-to-cell) in which the reference area and evaluation area are compared might make an erroneous judgment even when many etch pits are actually caused, because images that are much the same are compared, and it has thus been difficult to detect, count and evaluate the dislocations without omission.
It should be noted that the term “defect” is used in a broad sense in the present specification, and includes foreign particles (minute particles and film residuals) on the semiconductor wafer, abnormal shape portions, and portions having abnormalities in shape, light intensity and color.